1. Field of the Invention
The present invention relates to an input buffer of a semiconductor device, and in particular to an input buffer of a semiconductor device that generates an internal signal in response to an external signal and gives the internal signal to its internal circuit.
2. Description of the Background Art
FIG. 8 is a block diagram showing a conventional semiconductor memory device. In FIG. 8, this device has a control signal buffer 51, an address buffer 52, a clock buffer 53, a data output buffer 54 and a data input buffer 55.
The control signal buffer 51 transmits an external control signal CNT including a plural-bit signal to an internal circuit 56. By the external control signal CNT, various commands such as a read command and a write command are given to the internal circuit 56.
The address buffer 52 transmits an external address signal ADD including a plural-bit signal to the internal circuit 56. The internal circuit 56 includes memory cells, each of which a specific address is assigned to. By the external address signal ADD, any one of the memory cells is designated. The clock buffer 53 synchronizes with external clock signals CLK and /CLT to generate a signal for designating output timing of data and then give the signal to the internal circuit 56.
In response to a read command, the internal circuit 56 reads data in the memory cell designated by the external address signal ADD. In response to the signal from the clock buffer 53, the read data DO is outputted through the data output buffer 54 to the outside. Write data DI is given through the data input buffer 55 to the internal circuit 56. In response to a write command, the internal circuit 56 writes the data DI in the memory cell designated by the external address signal ADD.
FIG. 9 is a circuit diagram of the clock buffer 53. In FIG. 9, the clock buffer 53 includes P channel MOS transistors 61 and 62, and N channel MOS transistors 63 and 64. The MOS transistors 61-64 constitute a comparator for comparing the clock signal CLK with the clock signal /CLK complementary thereto so as to output a signal VO having a level corresponding to the result of the comparison.
In the case that the level of the clock signal CLK is lower than that of the clock signal /CLK, the electric current flowing through the MOS transistors 61-63 becomes smaller than that flowing through the MOS transistor 64 so that the signal VO is at an xe2x80x9cLxe2x80x9d level. In the case that the level of the clock signal CLK is higher than that of the clock signal /CLK, the electric current flowing through the MOS transistors 61-63 becomes larger than that flowing through the MOS transistor 64 so that the signal VO is at an xe2x80x9cHxe2x80x9d level. When the clock signal CLK is raised up from the xe2x80x9cLxe2x80x9d level (ground potential GND) to the xe2x80x9cHxe2x80x9d level (power source VCC) and the clock signal /CLK is fallen down from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level, the signal VO is raised from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cHxe2x80x9d level. The read data DI is outputted through the data output buffer 54 to the outside, in synchronization with the rising edge of the signal VO.
FIG. 10 is a circuit diagram of the data input buffer 55. In FIG. 10, the data input buffer 55 includes P channel MOS transistors 71 and 72, N channel MOS transistors 73 and 74, and an inverter 75. The MOS transistors 71-74 and the inverter 75 constitute a comparator for comparing the level of the external data signal DI with a reference potential VR (VCC/2) to output a signal VO corresponding to the result of the comparison.
In the case that the level of the data signal DI is lower than the reference potential VR, the electric current flowing through the MOS transistor 74 becomes smaller than that flowing through the MOS transistors 71-73 so that the signal VO is at the xe2x80x9cLxe2x80x9d level. In the case that the level of the data signal DI is higher than the reference potential VR, the electric current flowing through the MOS transistor 74 becomes larger than that flowing through the MOS transistors 71-73 so that the signal VO is at the xe2x80x9cHxe2x80x9d level. The signal VO is written in the selected memory cell in the external circuit 56.
However, such a conventional semiconductor memory device has the following problem.
FIGS. 11A and 11B are timing charts showing operation of the clock buffer 53 shown in FIG. 9. The clock signal CLK is raised up from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cHxe2x80x9d level and the clock signal /CLK is fallen down from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level, so that the signal VO is raised up from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cHxe2x80x9d level at the cross point where the clock signals CLK and /CLK cross each other. In this case, the response time for the rise from the xe2x80x9cLxe2x80x9d level of the signal VO to the midpoint level (VCC/2) thereof, which starts correspondingly to the cross point, varies dependently on the level of the cross point.
Specifically, the response time xcex94t1 in the case that the level of the cross point is higher than VCC/2 (FIG. 11A) is shorter than the response time xcex94t2 in the case that the level of the cross point is lower than VCC/2 (FIG. 11B). This is based on the following reason. As shown in FIG. 12, electric current I flowing through the N channel MOS transistors 63 and 64 is not in proportion to input potential VI (the level of the clock signals CLK and /CLK). Thus, when the input potential VI of the N channel MOS transistors 63 and 64 is high, the ratio of electric current variation xcex94I1 to potential variation xcex94V1 (i.e., xcex94I1/ xcex94V1) is relatively large. On the other hand, when the input potential VI of the N channel MOS transistors 63 and 64 is low, the ratio of electric current variation xcex94I2 to potential variation xcex94V2 (i.e., xcex94I2/ xcex94V2) is relatively small.
As described above, in conventional semiconductor memory devices, the response time of the signal VO, which starts correspondingly to the cross point of the clock signals CLK and /CLK, is scattered. Therefore, access time is also scattered so that the operation of the semiconductor memory devices is disturbed from being made speedy.
FIGS. 13 A and B are time charts of the data input buffer 55 shown in FIG. 10. The data signal DI is raised up from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cHxe2x80x9d level, so that the signal VO is raised up from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cHxe2x80x9d level at the cross point where the data signal DI and the reference potential VR cross each other. The data signal DI is fallen down from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level, so that the signal VO is fallen down from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level at the cross point where the data signal DI and the reference potential VR cross. In this case, the response time xcex94tH for the rise from the xe2x80x9cLxe2x80x9d level of the signal VO to the midpoint level thereof, which starts correspondingly to the cross point, is shorter than the response time xcex94tL for the fall from the xe2x80x9cHxe2x80x9d level of the signal VO to the midpoint level thereof, which starts correspondingly to the cross point.
This is based on the following reason. As shown in FIG. 14, electric current I flowing through the N channel transistor 74 is not in proportion to input potential VI (the level of the data signal DI). Thus, when the input potential VI of the N channel MOS transistor 74 is higher than the reference potential VR, the ratio of electric current variation xcex94IH to potential variation xcex94VH (i.e., xcex94IH/ xcex94VH) is relatively large. On the other hand, when the input potential VI of the N channel MOS transistor 74 is lower than the reference potential VR, the ratio of electric current variation xcex94IL to potential variation xcex94VL (i.e., xcex94IL/xcex94VL) is relatively small.
As described above, in conventional semiconductor memory devices, the response time of the signal VO in response to the external data signal DI is scattered. Therefore, long setup time and holding time are necessary. Thus, the operation of the semiconductor memory devices is disturbed from being made speedy.
Therefore, an object of the present invention is to provide an input buffer of a semiconductor device having a small scattering in delay time.
The input buffer of a semiconductor device according to one aspect of the present invention includes a first comparator including first and second transistors of first conduction type, input electrodes of which receive the external signal and a reference signal respectively, the first comparator changing a first signal from a first level to a second level in response to the fact that the level of the external signal exceeds the level of the reference signal; a second comparator including third and fourth transistors of second conduction type, input electrodes of which receive the external signal and the reference signal respectively, the second comparator changing a second signal from the first level to the second level in response to the fact that the level of the external signal exceeds the level of the reference signal; and a logic circuit that changes the internal signal from an inactive level to an active level in response to the fact that either one of the first or second signal turns into a third level between the first and second levels. Therefore, the internal signal is generated in response to the signal having a shorter response time among the first and second signals. Thus, even if the level of the cross point where the external signal and the reference signal cross, a scatter in the response time of the internal signal, which starts correspondingly to the cross point, can be suppressed and made small. As a result, the operation of the semiconductor device can be made speedy.
In a preferable embodiment, the first comparator changes the first signal from the second level to the first level in response to the fact that the level of the external signal becomes lower than the level of the reference signal. Furthermore, the second comparator changes the second signal from the second level to the first level in response to the fact that the level of the external signal becomes lower than the level of the reference signal. Furthermore, when the internal signal is at the inactive level, the logic circuit sets the internal signal to the active level in response to the fact that either one of the first or second signal turns into the third level, and when the internal signal is at the active level, the logic circuit sets the internal signal to the inactive level in response to the fact that either one of the first or second signal turns into the third level. In this case, a scatter in the response time of the internal signal, which starts correspondingly to the cross point, can be suppressed and made small even if the internal signal is changed from the active level to the inactive level.
In another preferable embodiment, the reference signal is a signal complementary to the external signal. In this case, the level of the internal signal changes correspondingly to the cross point where the external signal and the signal complementary thereto cross.
In a further preferable embodiment, one level of the external signals is equal to the first potential, and the other level is equal to the second potential. Furthermore, the reference signal is fixed to a third potential between the first and second potentials. In this case, the level of the internal signal changes correspondingly to the cross point where the external signal and the third potential cross.
In a still further embodiment, the first comparator further includes a first current mirror circuit connected to the first and second transistors. The current mirror circuit sets the first signal to the first level when a first electric current flowing through the first transistor is smaller than a second electric current flowing through the second transistor, and sets the first signal to the second level when the first electric current is larger than the second electric current. Furthermore, the second comparator further includes a second current mirror circuit connected to the third and fourth transistors. The second current mirror circuit sets the second signal to the first level when a third electric current flowing through the third transistor is larger than a fourth electric current flowing through the fourth transistor, and sets the second signal to the second level when the third electric current is smaller than the fourth electric current. In this case, the first and second comparators can easily be made.
The input buffer of a semiconductor device according to another aspect of the present invention includes a first comparator including first and second transistors of first conduction type, input electrodes of which receive the external signal and a reference potential respectively, the first comparator comparing the level of the external signal with the reference potential to output a signal having a level corresponding to the comparison result; a second comparator including third and fourth transistors of second conduction type, input electrodes of which receive the external signal and the reference potential respectively, the second comparator comparing the level of the external signal with the reference potential to output a signal having a level corresponding to the comparison result; and a selection logic circuit that receives output signals of the first and second comparators, selects the output signal of the first comparator when the external signal changes from the first level to the second level, and selects the output signal of the second comparator when the external signal changes from the second level to the first level, so as to change the level of the internal signal in response to the fact that the level of the selected signal changes. Therefore, it is possible to make the response time in the case that the external signal changes from the first level to the second level consistent with the external potential changes from the second level to the first level. As a result, the operation of the semiconductor device can be made speedy.
In a preferable embodiment, the selection logic circuit selects the output signal of either one of the first or second comparator on the basis of combination of the levels of the output signals of the first and second comparators immediately before the level of the external signal changes. In this case, the level of the internal signal changes correspondingly to change in the level of the output signal of the comparator selected on the basis of combination of the levels of the output signals of the first and second comparators.
In another preferable embodiment, the selection logic circuit receives the internal signal to select the output signal of either one of the first or second comparator on the basis of the level of the internal signal. In this case, the level of the internal signal changes correspondingly to change in the level of the output signal of the comparator selected on the basis of the level of the internal signal.
The foregoing and other objects, features, aspects and advantages of the present invention will becomes more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.